1) Technical Field of the Invention
The present invention relates to a semiconductor device used for an inverter device, and in particular, relates to the semiconductor device suppressing an operation of a parasitic transistor, thereby reducing the power loss and improving the ruggedness.
2) Description of Related Arts
An inverter device uses a half-bridge circuit including an Insulated Gate Bipolar Transistor (IGBT) and a Free Wheel Diode reversely connected in parallel. In the art of the present invention, several semiconductor devices used for the inverter device have been proposed.
For example, a Japanese Patent Laid-Open Publication Application JPA 2001-332729 discloses a transistor operating in a bipolar mode which can reduce ON-resistance while reducing a turn-off loss even at high temperature by controlling thickness and peak impurity concentration of an n-type buffer layer and a p-type emitter layer.
Also, according to another Japanese Patent Laid-Open Publication Application JPA 2002-299623, a high breakdown-voltage semiconductor device is proposed, in which the conduction power loss can be stabilized. The ratio of the impurity quantity doped within the n-type buffer layer to the impurity quantity doped within the p-type emitter layer falls within a range from 2.5 through 8.2 so as to reduce the variation of the conduction power loss even when the impurity quantity of those layers substantially vary.
Further, another Japanese Patent Laid-Open Publication Application JPA 04-240775 provides a triode semiconductor device including an emitter short-circuit structure having a buffer layer intervened between an anode-emitter region and a base region, thereby to improve the trade-off relationship between turn-on and turn-off characteristics.
In addition, another Japanese Patent Laid-Open Publication Application JPA 10-050724 suggests an IGBT having a short-lifetime region obtained by an ion radiation, in which the ion radiation is processed substantially across the undepleted region so as to suppress a tail current at a low voltage without reducing the breakdown voltage and increasing leakage current and ON-voltage.
As above, the inverter device used for electric trains or industries incorporates the IGBT of a high breakdown voltage which may exceed 4.5 kV, and includes a fairly thick n-type drift layer for ensuring the high breakdown voltage. Still, a transient ON-voltage applied across the FWD due to the electromotive force of the inductive load may be raised up to several hundreds volts higher than the reverse breakdown voltage of the IGBT, which allows the reverse current from the emitter to collector electrode. Thus, the transient ON-voltage across the FWD may severely affect the induction load operation of the IGBT.
FIG. 14 illustrates a circuit diagram of a conventional power converting circuit incorporating a half-bridge circuit structure. FIG. 15 shows a set of timing diagrams of outputs when the half-bridge circuit structure is used for the induction load.
In the half-bridge circuit structure of FIG. 14, when the IGBT 2 turns off (switching from ON-state to OFF-state, i.e., Stage II to Stage III), a forward voltage is applied across the FWD and a forward current (recovery current) I1 runs through the FWD. Such a forward voltage has the transient voltage up to several hundreds volts, thus, the IGBT 1 having insufficient reverse breakdown voltage may have an avalanche current I2 from the emitter to collector electrode with the transient voltage applied thereto.
After the recovery operation of the FWD, when the IGBT 2 again turns on (switching from OFF-state to ON-state, i.e., Stage III to Stage IV), the avalanche current I2 serves as a base-current of a parasitic pnp transistor (pnp-Tr) triggering the parasitic pnp-Tr current running through the IGBT 1. In conjunction with the recovery current of the FWD, the parasitic pnp-Tr current leads the power loss of the IGBT 1, the turn-off loss of the power converting circuit (IGBT 2), and the recovery loss of the IGBT 1 and the FWD.
The present inventors addresses the aforementioned problems by suppressing the parasitic pnp-Tr current of the IGBT with two approaches as indicated below;
a) The reverse breakdown voltage of the IGBT is improved to suppress the avalanche current I2 of the IGBT 1 generated at the turning-on of the IGBT 2 (Stage III), which serves as the base-current of a parasitic pnp-Tr triggering the parasitic pnp-Tr current of the IGBT 1.
b) Even where the avalanche current I2, i.e., the base-current of the parasitic pnp-Tr is generated, the parasitic pnp-Tr is not likely to be acted or switched on. In particular, the IGBT is provided with a short carrier-lifetime region to the extent not to increase the operating voltage of the IGBT.